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Bit
Name
Reset
Access
Description
Value
2
Mode
FRAMESTART
Description
The data transfer is done continously at every LCD frame start
0
EN
0
RW
LCD Enable
When this bit is set, the LCD driver is enabled and the driver will start outputting waveforms on the com/segment lines.
29.5.2 LCD_DISPCTRL - Display Control Register
Offset
0x004
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:21
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
20:18
VBLEV
0x3
RW
Voltage Boost Level
These bits control Voltage Boost level. Please refer to datasheet for further details of the boost levels.
Value
0
1
2
3
4
5
6
7
Mode
LEVEL0
LEVEL1
LEVEL2
LEVEL3
LEVEL4
LEVEL5
LEVEL6
LEVEL7
Description
Minimum boost level
Maximum boost level
17
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
16
VLCDSEL
0
RW
V LCD Selection
This bit controls which Voltage source that is connected to V LCD .
Value
0
1
Mode
VDD
VEXTBOOST
Description
VDD
Voltage Booster/External VDD
15
CONCONF
0
RW
Contrast Configuration
This bit selects whether the contrast adjustment is done relative to V LCD or Ground.
Value
0
1
Mode
VLCD
GND
Description
Contrast is adjusted relative to V LCD
Contrast is adjusted relative to Ground
14:13
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
12:8
CONLEV
0x1F
RW
Contrast Level
These bits control the contrast setting according to this formula: V LCD_OUT = V LCD × 0.5(1+CONLEV/31).
Value
0
31
Mode
MIN
MAX
Description
Minimum contrast
Maximum contrast
7:5
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
2011-04-12 - d0001_Rev1.10
436
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